out and ignored, as shown in Figure 2-4.
In Figure 2-4, the source1 field specifies the register containing the
memory address that the processor is to load data from, and the destination
field specifies the register that the loaded data is to be placed in.
The Mechanics of Program Execution
23
0
1
2
3
4
5
6
7
mode
opcode
source1
00
Byte 1
8
9
10
11
12
13
14
15
destination
000000
Byte 2
Figure 2-4: Machine language format for a register-type load
For a register-relative addressed load, we use a version of the immediate-
type instruction format, shown in Figure 2-5, with the base field specifying
the register that contains the base address and the offset stored in the second
byte of the instruction.
0
1
2
3
4
5
6
7
mode
opcode
base
destination
Byte 1
8
9
10
11
12
13
14
15
8-bit immediate offset
Byte 2
Figure 2-5: Machine language format for a register-relative load
Recall from Table 2-2 that 00 is the binary number that designates
register A. Therefore, as a result of the DLW-1’s particular machine language
encoding scheme, any register but A could theoretically be used to store the
base address for a register-relative load.
The store Instruction
The register-type binary format for a store instruction is the same as it is for a load, except that the destination field specifies a register containing a destination memory address, and the source1 field specifies the register contain-
ing the data to be stored to memory.
The immediate-type machine language format for a store, pictured in
Figure 2-6, is also similar to the immediate-type format for a load, except that since the destination register is not needed (the destination is the immediate
memory address) the destination field is zeroed out, while the source field
specifies which register holds the data to be stored.
24
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itm02_03.fm Page 25 Thursday, January 11, 2007 10:44 AM
0
1
2
3
4
5
6
7
mode
opcode
source
00
Byte 1
8
9
10
11
12
13
14
15
8-bit immediate destination address
Byte 2
Figure 2-6: Machine language format for an immediate-type store
The register-relative store, on the other hand, uses the same immediate-
type instruction format used for the register-relative load (Figure 2-5), but
the destination field is set to a nonzero value, and the offset is stored in the second byte. Again, the base address for a register-relative store can theoretically be stored in any register other than A, although by convention it’s
stored in D.
Translating an Example Program into Machine Language
For our simple computer with four registers, three instructions, and 256
memory cells, it’s tedious but trivial to translate Program 1-1 into machine-
readable binary representation using the previous tables and instruction
formats. Program 2-1 shows the translation.
Line
Assembly Language
Machine Language
1
load #12, A
10100000 00001100
2
load #13, B
10100001 00001101
3
add A, B, C
00000001 10000000
4
store C, #14
10111000 00001110
Program 2-1: A translation of Program 1-1 into machine language
The 1s and 0s in the rightmost column of Program 2-1 represent the
high and low voltages that the computer “thinks” in.
Real machine language instructions are usually longer and more complex
than the simple ones I’ve given here, but the basic idea is exactly the same.
Program instructions are translated into machine language in a mechanical,
predefined manner, and even in the case of a fully modern microprocessor,
doing such translations by hand is merely a matter of knowing the instruction
formats and having access to the right charts and tables.
Of course, for the most part the only people who do such translations by
hand are computer engineering or computer science undergraduates who’ve
been assigned them for homework. This wasn’t always the case, though.
The Mechanics of Program Execution
25
The Programming Model and the ISA
Back in the
Celine Roberts
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William W. Johnstone
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